One Board, 632% More Capacitors

The clearest data point of the week comes from a single accelerator. A single AMD MI450 board went from 1,440 to 10,544 MLCCs - a 632% increase on one component class - by replacing aluminum electrolytics and tantalum caps with all-MLCC solutions. That is what the transition to 48V and 800V power architectures on AI boards looks like at the bill-of-materials level: an irreplaceable jump in high-capacitance, small-footprint ceramic content.

The supply side is reacting in kind. Murata's book-to-bill ratio hit 1.27 - a post-pandemic high - with one supplier-side characterization of demand as simply "scary." Lead times for 0402 and 0201 high-density MLCCs stretch to 52 weeks, and Japanese and Korean suppliers are prioritizing server-grade parts, pulling capacity away from consumer-grade components.

This is structural, not cyclical. It is driven by a power-architecture transition that does not reverse, and it will not resolve in 2026.

Unbuildable Boards

The constraint has spread well beyond ceramics. Sourcing communities are now reporting "unbuildable boards" - assemblies held up not by their CPUs or GPUs but by the auxiliary parts around them:

  • High-temperature connector resins with extended lead times
  • High-frequency PCB substrates in short supply
  • Specialized passives competing with server demand
  • Epoxy lead times at 15 weeks
  • PCB costs up 10-25% standard, and up to 40% for complex HDI builds
  • Copper above $10,000 per metric ton, feeding straight into board and foil costs

The board that ships is gated by its weakest, cheapest line item - and right now that line item is a passive or a substrate, not a processor.

The Planning Error to Avoid

The instinct is to protect the expensive parts on the BOM - the accelerators, the memory, the FPGAs - and assume the passives will sort themselves out. That assumption is exactly what turns into a line-down event. A single-sourced high-capacitance MLCC with no qualified alternate is not a risk line on a spreadsheet; it is a stoppage waiting for a date.

The teams staying ahead are mapping the sub-tier BOM alongside the major ICs and designing multi-footprint layouts from day one - not retrofitting them after a 52-week quote lands.

What Buyers Should Do Now

  1. Next 7 days: Scrub BOMs and AVLs for single-source exposure on high-capacitance MLCCs (10uF/20uF, 0402/0201) and specialized high-frequency PCB substrates. Every one-supplier, no-alternate part is a line-down candidate - flag it now.
  2. Next 30 days: Partner with engineering to qualify multi-footprint layouts and alternate passives as design-approved, and map the sub-tier BOM alongside the major ICs so nothing is flying blind.
  3. Next 90 days: Lock rolling capacity agreements for high-capacitance passives and high-frequency substrates so AI-server demand cannot cannibalize your allocation.